Method for low temperature selective growth of silicon or silicon alloys

ABSTRACT

Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and then growing the epitaxial layer over the wafer at temperatures below 650° C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650° C. by providing a lower temperature process.

This application is a division of application Ser. No. 08/240,060, filed May 9, 1994, now U.S. Pat. No. 5,427,630.

FIELD OF THE INVENTION

The present invention relates to semiconductor devices, and more particularly, to masking materials for low temperature selective growth of epitaxial layers.

BACKGROUND OF THE INVENTION

Selective epitaxial growth (SEG) of silicon and silicon-germanium alloy layers can be used in both CMOS and bipolar semiconductor devices. In the SEG method, the epitaxial layer is selectively grown only on an exposed silicon surface and not on the field area of the device. This selective deposition results in a device structure having fine dimensional isolation with high aspect ratio geometry and small effective channel-width deviation from the design width. As a result, reduction of chip size and area (with CMOS devices) is achieved.

Known methods of selectively growing epitaxial silicon layers involve using a masking layer, generally silicon dioxide, to prevent growth of the epitaxial layer on the field areas. A number of methods are known for selectively growing epitaxial silicon with respect to silicon dioxide using SiH₂ Cl₂ /HCl or SiCl₄ /H₂ chemistry with either atmospheric or low pressure chemical deposition techniques.

In all of the known methods, however, the process temperature for the epitaxial layer deposition is always in the range of 650° to 1100° C. These high temperatures cause problems such as greater stress, silicon warping, deformation of fine structures, degradation of doping profile, and overall thermal degradation of the semiconductor device. As understood, no such process is presently known for the selective growth of an epitaxial silicon layer at temperatures below 650° C.

SUMMARY OF THE INVENTION

An epitaxial layer is selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from the group consisting of scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium. The epitaxial layer is then grown over the wafer at temperatures below 650° C., but it does not grow on the masking layer.

DESCRIPTION OF THE DRAWINGS

FIGS. 1(a)-1(d) are cross sectional views illustrating selective low temperature epitaxial growth on a semiconductor wafer using an exemplary masking material of the present invention.

FIGS. 2(a)-2(c) are cross sectional views illustrating selective low temperature polycrystalline growth on an intermediate layer on a semiconductor wafer using an exemplary masking material of the present invention.

FIG. 3 is a cross sectional view illustrating low temperature polycrystalline growth on an intermediate layer on a semiconductor wafer.

FIG. 4 is a cross sectional view illustrating low temperature epitaxial growth on a semiconductor wafer.

FIG. 5(a) is a Rutherford backscattering spectroscopy (RBS) plot of the examples illustrated in FIGS. 1(a)-1(d) and 2(a)-2(c). FIG. 5(b) is an RBS plot of the examples illustrated in FIGS. 3 and 4.

FIG. 6(a) is an optical micrograph of the examples illustrated in FIGS. 1(a)-1(d) , 2(a)-2(c), 3, and 4 after deposition of the epitaxial or polycrystalline layer. FIG. 6(b) is an optical micrograph of the examples illustrated in FIGS. 1(a)-1(d), 2(a)-2(c), 3, and 4 after an HCl:H₂ O etch used to remove the masking layer.

DETAILED DESCRIPTION

An exemplary embodiment of the present invention will now be described more fully with reference to the accompanying figures, in which growth of an epitaxial layer is illustrated and analyzed. FIGS. 1(a)-1(d) and 2(a)-2(c) illustrate the effectiveness of an exemplary masking layer according to the present invention to produce selective epitaxial growth at low temperature (below 650° C.) except in FIG. 2 which shows a polycrystalline growth. FIGS. 3 and 4 illustrate low temperature polycrystalline growth over an intermediate layer on a semiconductor substrate or wafer and epitaxial growth on the semiconductor wafer itself. These figures are purely schematic and are not drawn to scale. FIGS. 5(a), 5(b), 6(a), and 6(b) are analyses of the structures illustrated in the other figures.

An epitaxial layer can be selectively grown on a semiconductor substrate or wafer at low temperature in accordance with an exemplary embodiment of the present invention, in the following manner.

As shown in FIG. 1(a), the starting material is a semiconductor substrate or wafer 10. This wafer may be a material such as silicon, silicon carbide, germanium, and compounds and alloys thereof . It will be understood that the exact size and shape of the substrate or wafer is not of critical importance and may be selected to permit the formation thereon of the desired number of circuit elements.

A masking layer 11, e.g. yttrium oxide (Y₂ O₃) is deposited over wafer 10 in a desired pattern as shown in FIG. 1(b). The oxide deposition can be accomplished by known physical vapor deposition techniques such as sputtering, or by known chemical vapor deposition techniques, and any desired pattern can be generated using lithography (optical or e-beam).

An epitaxial layer 12, e.g. silicon, is grown over wafer 10 with patterned oxide masking layer 11. Epitaxial layer 12 (FIG. 1(c)), which may also be a silicon-germanium alloy, is grown by chemical vapor growth techniques. The deposition is carried out at temperatures below 650° C. U.S. Pat. No. 5,298,452, which is assigned to the same assignee as this application and is incorporated into this application by reference, describes a process for low temperature epitaxial deposition of silicon layers. A technique such as RBS or optical micrography can be used to confirm that epitaxial layer 12 does not grow on oxide masking layer 11. Oxide masking layer 11 is then etched off, using for example an HCl:H₂ O solution, to yield exemplary desired structure 13 as shown in FIG. 1(d).

Oxide masking layer 11 is also an effective masking layer over intermediate layer 14, e.g. a dielectric material such as silicon dioxide (SiOn) or (Si₃ N₄), formed on semiconductor wafer 10, as shown in FIG. 2(a). Intermediate layer 14 can be formed using techniques well-known in the art that need not be described in detail.

Oxide masking layer 11, e.g. Y₂ O₃, is patterned over intermediate layer 14 according to the same techniques described above. Subsequently, as shown in FIG. 2(b), polycrystalline layer 15, e.g. silicon, is deposited over the structure shown in FIG. 2(a). Although some lateral overgrowth of polycrystalline layer 15 across oxide masking layer 11 is observed, RBS and optical micrography confirm that polycrystalline layer 15 in fact grows selectively; that is, it does not grow on oxide masking layer 11. Oxide masking layer 11 is then etched off as above to yield the structure shown in FIG. 2(c).

As shown in FIG. 3, under the same epitaxial deposition conditions described above, at temperatures below 650° C., polycrystalline layer 15 does grow on intermediate layer 14 formed over wafer 10 without masking layer 11. Although silicon dioxide acts as a masking material at temperatures above 650° C., at the lower temperature UHV-CVD process involved in this invention, polycrystalline growth occurs on the silicon dioxide. Similarly, epitaxial layer 12 grows on wafer 10 at the conditions described in this invention, and results in a structure as shown in FIG. 4.

EXAMPLE 1

A 100 nm thick Y₂ O₃ film 11 was deposited on an 82 mm diameter <100> Si wafer 10 (FIG. 1). Y₂ O₃ masking layer 11 was deposited using an MRC 643 side scan magnetron sputtering system from a planar oxide magnetron target. The base pressure of the MRC sputtering system was between 0.5 and 1×10E-7 Torr and the sputtering gas used was 99.9995% pure Ar mixed with 0.8-1.2% (99.995%) pure O₂. The gas composition was controlled with an optical gas analyzer. The O₂ was used to keep the Y₂)₃ target from becoming metallic. A radio frequency power of 1 KW was applied to the Y₂ O₃ target giving a deposition rate of 1.33 nm per minute. The Y₂ O₃ deposition temperature was kept below 250° C. RBS and XRD confirmed that Y₂ O₃ film 11 was stoichiometric and crystalline.

Silicon wafer 10 with Y₂ O₃ layer 11 was then given an HF dip and placed in an ultra high vacuum chemical vapor deposition (UHV-CVD) reactor for Si and Si₀.9 Ge₀.1 growth. One such reactor is described in U.S. Pat. No. 5,181,964, assigned to the same assignee as this application and incorporated into this application by reference. In the UHV-CVD reactor, the temperature was 550° C.; the pressure was 1 mTorr; the gas was a mixture of 100% silane at 1 sccm plus 10% Germane in He at 5 sccm; and the growth rate was in the range from 10-20 Å per minute and was practiced at 15 Å per minute. RBS was used to analyze the resultant structure. The results of this analysis, shown at 20 in FIG. 5(a), illustrate that no Si or Si₀.9 Ge₀.1 nucleated and grew on Y₂ O₃ film 11. An optical micrograph, 21 in FIG. 6(a), confirmed the absence of silicon on the Y₂ O₃ layer.

EXAMPLE 2

Using the same sputtering system as described above, a 100 nm thick Y₂ O₃ film was deposited on an approximately 400 nm thick layer of SiO₂ formed by thermal oxidation on silicon wafer 10 (FIG. 2). The resultant structure was then placed in the UHV-CVD reactor for 140 nm Si₀.9 Ge₀.1 growth followed by 100 nm Si growth. The same layer deposition conditions as described above were used in this example. Once again, RBS was used to analyze the resultant structure. As shown at 30 in FIG. 5(a), no Si or Si₀.9 Ge₀.1 nucleated and grew on the Y₂ O₃ film. An optical micrograph confirmed the absence of silicon (with the exception of some lateral overgrowth) as illustrated at 31 in FIG. 6(a).

EXAMPLE 3

To illustrate the effectiveness of Y₂ O₃ as a masking layer, a blanket Si wafer 10 was used as a control (FIG. 4). No Y₂ O₃ layer was deposited on this substrate. After being given a HF dip, the Si wafer was exposed to UHV-CVD epitaxial growth of 140 nm Si₀.9 Ge₀.1 followed by 100 nm Si growth. The conditions for this deposition were the same as those described in the examples above. RBS was used to determine that Si 100 nm thick and Si₀.9 Ge₀.1 140 nm thick in fact nucleated and grew on the Si substrate, as shown at 40 in FIG. 5(b). An optical micrograph confirmed the growth of epitaxial silicon on the silicon as shown at 41 in FIG. 6(a) .

EXAMPLE 4

As another control, Si wafer 10 with a 400 nm thick layer of SiO₂ 14 (FIG. 3) formed thereon was subjected to UHV-CVD deposition of polycrystalline Si₀.9 Ge₀.1 and Si growth. The conditions were the same for this deposition as those described in the examples above. RBS was used to analyze the resulting structure and determined that polycrystalline Si 100 nm thick and Si₀.9 Ge₀.1 140 nm thick did in fact nucleate and grow on SiO₂ layer 14. This is illustrated at 50 in FIG. 5(b). An optical micrograph confirmed the presence of polycrystalline silicon over the SiO₂ layer, as shown at 51 in FIG. 6(a).

FIG. 6(b) is an optical micrograph of the above examples 1-4 after the samples were etched by an HCl:H₂ O mixture. The HCl:H₂ O mixture does not etch silicon or silicon dioxide; it only attacks the Y₂ O₃. The reference numerals in FIG. 6(b) correspond to those in FIG. 6(a) and refer to the same examples. As can be seen, once the Y₂ O₃ layer was etched off, at 21 only the original silicon substrate remains while at 31, only the SiO₂ layer remains. The fact that the Y₂ O₃ layer was so easily etched off of the SiO₂ layer at 31 is believed to prove that any polycrystalline Si that was observed over the Y₂ O₃ layer was lateral overgrowth resulting from the growth of polycrystalline Si on the SiO₂ layer. This is because this overgrowth area was easily undercut using the etch to remove the Y₂ O₃ and expose the SiOn.

The above examples were repeated on 125 mm diameter <100> Si and thermally oxidized <100> Si wafers. The same results for each example as reported above were achieved on these substrates.

Because yttrium is a Group IIIB element, and the Group IIIB elements, as well as the rare earth elements, all exhibit similar properties, it is reasonable to conclude that all Group IIIB oxides and rare earth oxides will act as a masking material for the selective growth of UHV-CVD epitaxial layers at temperatures below 650° C. The oxides of all of these elements are thus within the scope of the present invention, with the exception of actinium oxide and promethium oxide since actinium and promethium are radioactive. The following prophetic examples are submitted as disclosure of the other elements.

PROPHETIC EXAMPLE 1

Sc₂ O₃ is patterned on a semiconductor substrate for example silicon in accordance with the sputtering technique described in the above examples. After an HF dip, the wafer with the Sc₂ O₃ masking layer is then placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growth followed by 100 nm Si growth under the same conditions as those described in the above examples. RBS and optical micrographs would confirm that there is no nucleation or growth of epitaxial Si or Si₀.9 Ge₀.1 on the Sc₂ O₃ layer.

PROPHETIC EXAMPLE 2

La₂ O₃ is patterned on a semiconductor substrate for example silicon in accordance with the sputtering technique described in the above examples. After an HF dip, the wafer with the La₂ O₃ masking layer is then placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growth followed by 100 nm Si growth under the same conditions as those described in the above examples. RBS and optical micrographs would confirm that there is no nucleation or growth of epitaxial Si or Si₀.9 Ge₀.1 on the La₂ O₃ layer.

PROPHETIC EXAMPLE 3

CeO₂ is patterned on a semiconductor substrate for example silicon in accordance with the sputtering technique described in the above examples. After an HF dip, the wafer with the CeO₂ masking layer is then placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growth followed by 100 nm Si growth under the same conditions as those described in the above examples. RBS and optical micrographs would confirm that there is no nucleation or growth of epitaxial Si or Si₀.9 Ge₀.1 on the CeO₂ layer.

PROPHETIC EXAMPLE 4

Pr₂ O₃ is patterned on a semiconductor substrate for example silicon in accordance with the sputtering technique described in the above examples. After an HF dip, the wafer with the Pr₂ O₃ masking layer is then placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growth followed by 100 nm Si growth under the same conditions as those described in the above examples. RBS and optical micrographs would confirm that there is no nucleation or growth of epitaxial Si or Si₀.9 Ge₀.1 on the Pr₂ O₃ layer.

PROPHETIC EXAMPLE 5

Nd₂ O₃ is patterned on a semiconductor substrate for example silicon in accordance with the sputtering technique described in the above examples. After an HF dip, the wafer with the Nd₂ O₃ masking layer is then placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growth followed by 100 nm Si growth under the same conditions as those described in the above examples. RBS and optical micrographs would confirm that there is no nucleation or growth of epitaxial Si or Si₀.9 Ge₀.1 on the Nd₂ O₃ layer.

PROPHETIC EXAMPLE 6

Sm₂ O₃ is patterned on a semiconductor substrate for example silicon in accordance with the sputtering technique described in the above examples. After an HF dip, the wafer with the Sm₂ O₃ masking layer is then placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growth followed by 100 nm Si growth under the same conditions as those described in the above examples. RBS and optical micrographs would confirm that there is no nucleation or growth of epitaxial Si or Si₀.9 Ge₀.1 on the Sm₂ O₃ layer.

PROPHETIC EXAMPLE 7

Eu₂ O₃ is patterned on a semiconductor substrate for example silicon in accordance with the sputtering technique described in the above examples. After an HF dip, the wafer with the Eu₂ O₃ masking layer is then placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growth followed by 100 nm Si growth under the same conditions as those described in the above examples. RBS and optical micrographs would confirm that there is no nucleation or growth of epitaxial Si or Si₀.9 Ge₀.1 on the Eu₂ O₃ layer.

PROPHETIC EXAMPLE 8

Gd₂ O₃ is patterned on a semiconductor substrate for example silicon in accordance with the sputtering technique described in the above examples. After an HF dip, the wafer with the Gd₂ O₃ masking layer is then placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growth followed by 100 nm Si growth under the same conditions as those described in the above examples. RBS and optical micrographs would confirm that there is no nucleation or growth of epitaxial Si or Si₀.9 Ge₀.1 on the Gd₂ O₃ layer.

PROPHETIC EXAMPLE 9

Tb₂ O₃ is patterned on a semiconductor substrate for example silicon in accordance with the sputtering technique described in the above examples. After an HF dip, the wafer with the Tb₂ O₃ masking layer is then placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growth followed by 100 nm Si growth under the same conditions as those described in the above examples. RBS and optical micrographs would confirm that there is no nucleation or growth of epitaxial Si or Si₀.9 Ge₀.1 on the Tb₂ O₃ layer.

PROPHETIC EXAMPLE 10

Dy₂ O₃ is patterned on a semiconductor substrate for example silicon in accordance with the sputtering technique described in the above examples. After an HF dip, the wafer with the Dy₂ O₃ masking layer is then placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growth followed by 100 nm Si growth under the same conditions as those described in the above examples. RBS and optical micrographs would confirm that there is no nucleation or growth of epitaxial Si or Si₀.9 Ge₀.1 on the Dy₂ O₃ layer.

PROPHETIC EXAMPLE 11

Ho₂ O₃ is patterned on a semiconductor substrate for example silicon in accordance with the sputtering technique described in the above examples. After an HF dip, the wafer with the Ho₂ O₃ masking layer is then placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growth followed by 100 nm Si growth under the same conditions as those described in the above examples. RBS and optical micrographs would confirm that there is no nucleation or growth of epitaxial Si or Si₀.9 Ge₀.1 on the Ho₂ O₃ layer.

PROPHETIC EXAMPLE 12

Er₂ O₃ is patterned on a semiconductor substrate for example silicon in accordance with the sputtering technique described in the above examples. After an HF dip, the wafer with the Er₂ O₃ masking layer is then placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growth followed by 100 nm Si growth under the same conditions as those described in the above examples. RBS and optical micrographs would confirm that there is no nucleation or growth of epitaxial Si or Si₀.9 Ge₀.1 on the Er₂ O₃ layer.

PROPHETIC EXAMPLE 13

Tm₂ O₃ is patterned on a semiconductor substrate for example silicon in accordance with the sputtering technique described in the above examples. After an HF dip, the wafer with the Tm₂ O₃ masking layer is then placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growth followed by 100 nm Si growth under the same conditions as those described in the above examples. RBS and optical micrographs would confirm that there is no nucleation or growth of epitaxial Si or Si₀.9 Ge₀.1 on the Tm₂ O₃ layer.

PROPHETIC EXAMPLE 14

Yb₂ O₃ is patterned on a semiconductor substrate for example silicon in accordance with the sputtering technique described in the above examples. After an HF dip, the wafer with the Yb₂ O₃ masking layer is then placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growth followed by 100 nm Si growth under the same conditions as those described in the above examples. RBS and optical micrographs would confirm that there is no nucleation or growth of epitaxial Si or Si₀.9 Ge₀.1 on the Yb₂ O₃ layer.

PROPHETIC EXAMPLE 15

Lu₂ O₃ is patterned on a semiconductor substrate for example silicon in accordance with the sputtering technique described in the above examples. After an HF dip, the wafer with the Lu₂ O₃ masking layer is then placed in a UHV-CVD reactor for epitaxial 140 nm Si₀.9 Ge₀.1 growth followed by 100 nm Si growth under the same conditions as those described in the above examples. RBS and optical micrographs would confirm that there is no nucleation or growth of epitaxial Si or Si₀.9 Ge₀.1 on the Lu₂ O₃ layer.

While this invention has been described in terms of exemplary embodiments, it is contemplated that it may be practiced as outlined above with modifications within the spirit and scope of the appended claims. 

What is claimed:
 1. A method of selectively growing a layer over a semiconductor substrate comprising the steps of:(a) forming over said semiconductor substrate a mask of an oxide of an element selected from the group consisting of scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and (b) growing said layer over said semiconductor substrate at temperatures below 650° C., where said layer does not grow on said mask.
 2. A method of selectively growing an epitaxial layer on a semiconductor substrate, comprising the steps of:(a) forming over said wafer a masking layer of an oxide of an element selected from the group consisting of scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; (b) growing said epitaxial layer over said substrate at temperatures below 650° C., wherein said epitaxial layer does not grow on said masking layer.
 3. The method of claim 2 wherein said masking layer is a thin film masking layer in the range from 20 nm to 1000 nm.
 4. The method of claim 2 wherein said semiconductor substrate is selected from the group consisting of silicon, silicon carbide, germanium and compounds and alloys thereof.
 5. The method of claim 2 wherein said epitaxial layer is selected from the group consisting of silicon and silicon-germanium alloys.
 6. The method of claim 2 wherein said epitaxial layer is deposited by chemical vapor deposition.
 7. The method of claim 2 wherein said masking layer is formed by physical vapor deposition.
 8. The method of claim 2 wherein said masking layer is formed by sputtering.
 9. The method of claim 2 wherein said masking layer is formed by chemical vapor deposition.
 10. A method of selectively growing a polycrystalline layer on a semiconductor substrate, comprising the steps of:(a) depositing an intermediate layer over said substrate; (b) forming over said intermediate layer a masking layer of an oxide of an element selected from the group consisting of scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; (c) growing said polycrystalline layer over said substrate at temperatures below 650° C., wherein said polycrystalline layer does not grow on said masking layer.
 11. The method of claim 10 wherein said intermediate layer is a dielectric material.
 12. The method of claim 11 wherein said intermediate layer is selected from the group consisting of Si₃ N₄ and SiO₂.
 13. A process of manufacturing a semiconductor device comprising the steps of:(a) forming over a substrate a masking layer of an oxide of an element selected from the group consisting of scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; (b) growing an epitaxial layer over said substrate at a temperature below 650° C., wherein said epitaxial layer does not grow on said masking layer; and (c) etching off said masking layer.
 14. A process of manufacturing a semiconductor device comprising the steps of:(a) depositing an intermediate layer over a substrate; (b) forming over said intermediate layer a masking layer of an oxide of an element selected from the group consisting of scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; (c) growing a polycrystalline layer over said substrate at a temperatures below 650° C., wherein said epitaxial layer does not grow on said masking layer; and (d) etching off said masking layer. 